During fabrication of a semiconductor device, such as a semiconductor memory or logic device, a circuit layout can be generated from a circuit diagram of the semiconductor device. The circuit layout can be checked to ensure compliance with a specified set of design rules, which are a set of geometric constraints or rules that features in the circuit layout must conform to for a particular semiconductor manufacturing process. After the circuit layout has been checked to ensure compliance with the applicable set of design rules, the circuit layout can be transferred to a semiconductor wafer by using a lithographic process.
However, although the circuit layout conforms to applicable design rules, one section of the circuit layout may fail while another section of the circuit layout may not fail when the circuit layout is lithographically transferred to the semiconductor wafer. For example, a peripheral section of a memory circuit layout may fail while a core section of the memory circuit layout may not fail as a result of the peripheral and core sections of the memory circuit layout being lithographically transferred to the semiconductor wafer. Thus, even though the circuit layout conforms to applicable design rules, the circuit layout can fail as a result of being lithographically transferred to a wafer, which undesirably decreases manufacturing yield.
Thus, there is a need in the art for a method for determining whether a circuit layout that conforms to applicable design rules will fail as a result of being lithographically transferred to a wafer prior to transferring the circuit layout to the wafer.